VLSI Design & Technology Test Questions
VLSI Design & Technology Test Questions, this topic has 98 mcqs, It takes five to ten minutes to complete this free VLSI Design & Technology Test Questions test. You will see 4 or 5 option of each question. You must choose / think only one option and then press on answer key for check right answer. Practice "VLSI Design & Technology Test Questions" MCQs and share with your friends, brothers, sisters.
VLSI Design & Technology Test Questions (Total Quiz: 98)
MCQ: Which among the following is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type?
- Bit type
- Bit_vector type
- Boolean type
- All of the above
B
MCQ: In composite data type of VHDL, the record type comprises the elements of _______data types.
- Same
- Different
- Both a and b
- None of the above
B
MCQ: Which among the following wait statement execution causes the enclosing process to suspend and then wait for an event to occur on the signals?
- Wait until Clk = '1'
- Wait on x,y,z
- Wait on clock until answer > 80
- Wait for 12 ns
B
MCQ: After an initialization phase, the simulator enters the ______phase.
- Compilation
- Elaboration
- Execution
- None of the above
C
MCQ: Which concept proves to be beneficial in acquiring concurrency and order independence?
- Alpha delay
- Beta delay
- Gamma delay
- Delta delay
D
MCQ: An event is nothing but ______ target signal, which is to be updated.
- Fixed
- Change on
- Both a and b
- None of the above
B
MCQ: Which functions are performed by static timing analysis in simulation?
- Computation of delay for each timing path
- Logic analysis in a static manner
- Both a and b
- None of the above
C
MCQ: Which among the following is/are regarded as the function/s of translation step in synthesis process?
- Conversion of RTL description to boolean unoptimized description
- Conversion of an unoptimized to optimized boolean description
- Conversion of unoptimized boolean description to PLA format
- All of the above
A
MCQ: In synthesis flow, which stage/s is/are responsible for converting an unoptimized boolean description to PLA format?
- Translation
- Optimization
- Flattening
- All of the above
C
MCQ: In synthesis flow, the flattening process generates a flat signal representation of _____levels.
A. AND
B. OR
C. NOT
D. EX-OR
- A & B
- C & D
- A & C
- B & D
A