Digital Electronics Test Questions
Digital Electronics Test Questions, this topic has 81 mcqs, It takes five to ten minutes to complete this free Digital Electronics Test Questions test. You will see 4 or 5 option of each question. You must choose / think only one option and then press on answer key for check right answer. Practice "Digital Electronics Test Questions" MCQs and share with your friends, brothers, sisters.
Digital Electronics Test Questions (Total Quiz: 81)
MCQ: Which type of unipolar logic family exhibits its usability for the applications requiring low power consumption?
- PMOS
- NMOS
- CMOS
- All of the above
C
MCQ: Which type of output current flows towards or into the output terminal in a logic circuit?
- Sourcing current
- Sinking current
- Both a and b
- None of the above
B
MCQ: Suppose that the digital IC family has a fan out of 6. It implies that the gate can supply the current to _______ of same family.
- 6 inputs
- 6 outputs
- 12 nodes
- 12 branches
A
MCQ: What does the below stated OR Law imply, while performing OR operation of an input with '1'?
Expression of OR Law: A+ 1 = 1
- Output will always be equal to input
- Output will always be high
- Output will always be low
- Output will always be same
B
MCQ: How is the relation specified between input and output in logic circuits?
- Switching equations
- Truth-table
- Logic diagram
- All of the above
D
MCQ: In the half subtractor combinational circuit, what does 'A' represent in the subtraction operation (A - B)?
- Minuend bit
- Maxend bit
- Subtrahend bit
- Suptrahend bit
A
MCQ: Which is an incorrect rule of binary subtraction from the following?
- 0 – 0 = 0
- 0 – 1 = -1
- 1 – 0 = 1
- 0 – 1 = 1 with borrow '1'
B
MCQ: What should be the output of converter, if a common anode display segment is to be turned 'ON'?
- '0'
- '1'
- Both a and b
- None of the above
A
MCQ: Which adder plays a crucial role in eliminating the problem associated with the inter-stage carry delay?
- Half adder
- full adder
- BCD adder
- Look-ahead carry adder
D
MCQ: Which among the following is/are responsible for the occurrence of clock skew by introducing delays from different paths of clock generator to various circuits?
- Different length of wires
- Gates on the paths
- Gating of clock to control the loading of registers
- All of the above
D