MCQ: _________ is the fundamental architecture block or element of a target PLD.

1. System Partitioning
2. Pre-layout Simulation
3. Logic cell
4. Post-layout Simulation

MCQ: Basically, an observability of an internal circuit node is a degree to which one can observe that node at the _______ of an integrated circuit.

1. Inputs
2. Outputs
3. Both a and b
4. None of the above

MCQ: High observability indicates that ________number of cycles are required to measure the output node value.

1. More
2. Equal
3. Less
4. None of the above

MCQ: Due to the limitations of the testers, the functional test is usually performed at speed _______the target speed.

1. Lower than
2. Equal to
3. Greater than
4. None of the above

MCQ: Which among the following is/are responsible for the occurrence of 'Delay Faults'?

1. Variations in circuit delays & clock skews
2. Improper estimation of on-chip interconnect & routing delays
3. Aging effects & opens in metal lines connecting parallel transistors
4. All of the above

MCQ: Which among the following serves as an input stage to most of the op-amps due to its compatibility with IC technology?

1. Differential amplifier
2. Cascode amplifier
3. Operational transconductance amplifiers (OTAs)
4. Voltage operational amplifier